SH7785 Datasheet, PDF (734/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
Table 14.8 List of On-Chip Peripheral Module Request Modes
CHCR DMARS
DMA Transfer
RS[3:0] MID RID Request Source DMA Transfer Request Signal Source
1000
000000 11
SSI0 transmitter
Transmit data empty request Any
(In transmit mode, the DMRQ
bit in the SSISR0 register is 1.)
SSI0 receiver
Unread data is present (In
SSIRDR0
receive mode, the DMRQ bit in
the SSISR0 register is 1.)
000001 11
SSI1 transmitter
Transmit data empty request Any
(In transmit mode, the DMRQ
bit in the SSISR1 register is 1.)
SSI1 receiver
Unread data is present (In
SSIRDR1
receive mode, the DMRQ bit in
the SSISR1 register is 1.)
001000 01 SCIF0 transmitter TXI (transmit FIFO data empty) Any
10 SCIF0 receiver RXI (receive FIFO data full) SCFRDR0
001001 01 SCIF1 transmitter TXI (transmit FIFO data empty) Any
10 SCIF1 receiver RXI (receive FIFO data full) SCFRDR1
001010 01 SCIF2 transmitter TXI (transmit FIFO data empty) Any
10 SCIF2 receiver RXI (receive FIFO data full) SCFRDR2
001011 01 SCIF3 transmitter TXI (transmit FIFO data empty) Any
10 SCIF3 receiver RXI (receive FIFO data full) SCFRDR3
001100 01 SCIF4 transmitter TXI (transmit FIFO data empty) Any
10 SCIF4 receiver RXI (receive FIFO data full) SCFRDR4
Bus
Destination Mode
SSITDR0
Cycle
steal
Any
Cycle
steal
SSITDR1
Cycle
steal
Any
Cycle
steal
SCFTDR0
Any
SCFTDR1
Any
SCFTDR2
Any
SCFTDR3
Any
SCFTDR4
Any
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Rev.1.00 Jan. 10, 2008 Page 704 of 1658
REJ09B0261-0100