SH7785 Datasheet, PDF (710/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
14.3.6 DMA Transfer Count Registers B0 to B3, B6 to B9 (TCRB0 to TCRB3, TCRB6 to
TCRB9)
TCRB are 32-bit readable/writable registers. The data written to TCR by the CPU is also written
to TCRB. While the half end function is being used, TCRB are used as the initial value retain
registers to detect half end. Also, TCRB specify the number of DMA transfers which are set in
TCR again in repeat mode. TCRB specify the number of DMA transfers and are used as transfer
count counters in reload mode.
In reload mode, bits 7 to 0 operate as transfer count counters. When the values are 0, values of
SAR and DAR are updated, and the value of the bits 23 to 16 in TCRB are loaded to the bits 7 to
0. Set the number of transfers until reloading starts to bits 23 to 16. In reload mode, a value from
H'FF (255 times) to H'01 (1 time) can be specified to the bits 23 to 16 and 7 to 0 in TCRB, and set
the same number to bits 23 to 16 and bits 7 to 0 and set bits 15 to 8 to H'00. Also, clear the HIE bit
in CHCR to 0 and do not use the half end function.
Bits 31 to 24 in TCRB are always read as 0. The write value should always be 0.
The initial value of TCRB is undefined.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.1.00 Jan. 10, 2008 Page 680 of 1658
REJ09B0261-0100