SH7785 Datasheet, PDF (1165/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. Serial I/O with FIFO (SIOF)
The number of channels in control data is specified by the CD0E and CD1E bits in SICDAR.
Table 22.10 shows the relationship between the number of channels in control data and bit
settings.
Table 22.10 Number of Channels in Control Data
Number of Channels
CD0E
1
1
2
1
Note: To use only one channel in control data, use channel 0.
Bit
CD1E
0
1
22.4.5 Control Data Interface
Control data performs control command output to the CODEC and status input from the CODEC.
The SIOF supports the following two control data interface methods.
• Control by slot position
• Control by secondary FS
Control data is valid when data length is specified as 16 bits.
(1) Control by Slot Position (Master Mode 1 and Slave Mode 1)
Control data is transferred for all frames transmitted or received by the SIOF by specifying the slot
position of control data. This method can be used in both SIOF master and slave modes. Figure
22.7 shows an example of the control data interface timing by slot position control.
1 frame
SIOF_SCK
SIOF_SYNC
SIOF_TXD
SIOF_RXD
L-channel Control R-channel Control
data
channel 0
data
channel 0
Slot No.0 Slot No.1 Slot No.2 Slot No.3
Specifications: TRMD[1:0] = 00 or 10, REDG = 0
TDLE = 1,
TDLA[3:0] = 0000,
RDLE = 1,
RDLA[3:0] = 0000,
CD0E = 1,
CD0A[3:0] = 0001,
FL[3:0] = 1110 (Frame length: 128 bits),
TDRE = 1, TDRA[3:0] = 0010,
RDRE = 1, RDRA[3:0] = 0010,
CD1E = 1, CD1A[3:0] = 0011
Figure 22.7 Control Data Interface (Slot Position)
Rev.1.00 Jan. 10, 2008 Page 1135 of 1658
REJ09B0261-0100