SH7785 Datasheet, PDF (356/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
Interrupt
requests
Interrupt
requests
Priority
encoder
SH7785
IRQ/IRL3 to
IRL3 to IRL0 IRQ/IRL0
Priority
encoder
IRQ/IRL7 to
IRL7 to IRL4 ^IRQ/IRL4
Figure 10.3 Example of IRL Interrupt Connection
Table 10.12 IRL Interrupt Pins (IRL[3:0], IRL[7:4]) and Interrupt Levels
IRL3 or
IRL7
Low
Low
Low
Low
Low
Low
Low
Low
High
High
High
High
High
High
High
High
IRL2 or
IRL6
Low
Low
Low
Low
High
High
High
High
Low
Low
Low
Low
High
High
High
High
IRL1 or
IRL5
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
IRL0 or
IRL4
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Interrupt
Priority Level
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Interrupt Request
Level 15 interrupt request
Level 14 interrupt request
Level 13 interrupt request
Level 12 interrupt request
Level 11 interrupt request
Level 10 interrupt request
Level 9 interrupt request
Level 8 interrupt request
Level 7 interrupt request
Level 6 interrupt request
Level 5 interrupt request
Level 4 interrupt request
Level 3 interrupt request
Level 2 interrupt request
Level 1 interrupt request
No interrupt request
IRL interrupt detection requires an on-chip noise-cancellation feature. This detection is performed
when the level sampled at every bus clock is the same for three consecutive cycles. This detection
can prevent the incorrect level from being taking in when the IRL interrupt pin state changes.
Rev.1.00 Jan. 10, 2008 Page 326 of 1658
REJ09B0261-0100