SH7785 Datasheet, PDF (882/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
Bit
13, 12
11
10
9
8
7 to 0
Bit Name
⎯
Initial
Value
All 0
VBK
0
⎯
0
RINT
0
HBK
0
⎯
All 0
Internal
R/W Update Description
R
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
R
None Vertical Blanking Flag
0: Indicates the interval to the next display end
after clearing to 0 the VBK bit using either the
DRES bit in DSYSR or the VBCL bit in
DSRCR.
1: Indicates the interval, after clearing the VBK
bit using either the DRES bit in DSYSR or the
VBCL bit in DSRCR, from the first vertical
blanking interval until the VBK bit is again
cleared to 0. (field units)
R
⎯
Reserved
This bit is always read as 0. The write value
should always be 0.
R
None Raster Interrupt Flag
0: Indicates the interval from the start of the next
display until raster scans set in the raster
interrupt offset register have elapsed, after
clearing to 0 the RINT bit using either the
DRES bit in DSYSR or the RICL bit in
DSRCR.
1: After clearing the RINT bit using either the
DRES bit in DSYSR or the RICL bit in
DSRCR, indicates the interval from the start
of the next display after raster scans set in the
raster interrupt offset register have elapsed
until the bit is again cleared to 0.
R
None Horizontal Blanking Flag
0: Indicates the interval, after clearing to 0 the
HBK bit using the DRES bit in DSYSR or the
HBCL bit in DSRCR, to the next horizontal
blanking.
1: Indicates the interval, after clearing the HBK
bit using either the DRES bit in DSYSR or the
HBCL bit in DSRCR, from the first horizontal
blanking interval until the HBK bit is again
cleared to 0.
R
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev.1.00 Jan. 10, 2008 Page 852 of 1658
REJ09B0261-0100