SH7785 Datasheet, PDF (411/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Local Bus State Controller (LBSC)
Bit
3 to 0
Initial
Bit Name Value R/W
IW[3:0]
1111 R/W
Description
Insert Wait Cycle
These bits specify the number of wait cycles to be
inserted. The wait cycles are as follows when the
SRAM interface, byte control SRAM interface, burst
ROM interface (first data cycle only), or PCMCIA
interface is selected. Insertion of external wait cycles by
the RDY pin is not possible when "no cycle inserted" is
selected.
0000: No cycle inserted 1000: 8 cycles inserted
0001: 1 cycle inserted
1001: 9 cycles inserted
0010: 2 cycles inserted 1010: 11 cycles inserted
0011: 3 cycles inserted 1011: 13 cycles inserted
0100: 4 cycles inserted 1100: 15 cycles inserted
0101: 5 cycles inserted 1101: 17 cycles inserted
0110: 6 cycles inserted 1110: 21 cycles inserted
0111: 7 cycles inserted 1111: 25 cycles inserted
When MPX interface is selected, the wait cycles are
inserted as follows according to the IW[2:0] setting. The
IW[3] setting is invalid. The external wait cycles can be
inserted by the RDY pin in any settings.
IW[2] specifies wait cycle insertion for the second and
subsequent data:
0: No cycle inserted
1: 1 cycle inserted
IW[1:0] specifies wait cycle insertion for the first data:
00: 1 cycle inserted in reading and no cycle inserted in
writing
01: 1 cycle inserted in reading and 1 cycle inserted in
writing
10: 2 cycles inserted in reading and 2 cycles inserted in
writing
11: 3 cycles inserted in reading and 3 cycles inserted in
writing
Rev.1.00 Jan. 10, 2008 Page 381 of 1658
REJ09B0261-0100