SH7785 Datasheet, PDF (339/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
Initial
Bit Value R/W Source
30
R SCIF
channel 1
20
R SCIF
channel 0
10
R TMU
channels
3 to 5
00
R TMU
channels
0 to 2
Function
Description
SCIF channel 1 interrupt These bits indicate the interrupt
source indication
source of each peripheral module
SCIF channel 0 interrupt
that is generating an interrupt.
source indication
(INT2A1 is affected by the setting
of the interrupt mask register).
TMU channel 3 to 5 interrupt
source indication
0: No interrupt
1: An interrupt has occurred
TMU channel 0 to 2 interrupt ^{Note: Interrupt sources can also}
source indication
be identified by directly
reading the INTEVT code.
In this case, reading from
this register is not required.
If the interrupt source in an individual module is set or cleared, the time required until the state is
reflected in INT2A1 is as shown in table 10.7.
If the interrupt masking is set by INT2MSKR or the interrupt masking by INT2MSKR is cleared
by INT2MSKCLR, the reflection time required for INT2A1 is guaranteed by hardware. Therefore,
after the interrupt mask is set or cleared, the contents that reflect the setting of INT2MSKR can be
read.
Rev.1.00 Jan. 10, 2008 Page 309 of 1658
REJ09B0261-0100