SH7785 Datasheet, PDF (341/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
Initial
Bit Value R/W Source
Function
Description
18 1
17 1
16 1
15 1
14 1
13 1
12 1
11 1
R/W PCIC (4)
R/W PCIC (3)
Masks the PCIINTD interrupt
Masks the PCIINTC interrupt
Masks interrupt to each
on-chip peripheral
module
R/W PCIC (2)
Masks the PCIINTB interrupt
[When written]
R/W PCIC (1)
Masks the PCIINTA interrupt
0: Invalid
R/W PCIC (0)
Masks the PCISERR interrupt
1: Interrupts are masked
[When read]
R/W HAC channel 1 Masks the HAC channel 1 interrupt
0: Not masked
R/W HAC channel 0 Masks the HAC channel 0 interrupt _{1: Masked}
R/W DMAC (1)
Masks DMAC channels 6 to 11
interrupts and address error
interrupt
10 1
R/W DMAC (0)
Masks DMAC channels 0 to 5
interrupts and address error
interrupt
91
R/W H-UDI
Masks the H-UDI interrupt
81
R/W WDT
Masks the WDT interrupt
71
R/W SCIF channel 5 Masks SCIF channel 5 interrupt
61
R/W SCIF channel 4 Masks SCIF channel 4 interrupt
51
R/W SCIF channel 3 Masks SCIF channel 3 interrupt
41
R/W SCIF channel 2 Masks SCIF channel 2 interrupt
31
R/W SCIF channel 1 Masks SCIF channel 1 interrupt
21
R/W SCIF channel 0 Masks SCIF channel 0 interrupt
11
R/W TMU channels Masks TMU channels 3 to 5
3 to 5
interrupts
01
R/W TMU channels Masks TMU channels 0 to 2
0 to 2
interrupts
Rev.1.00 Jan. 10, 2008 Page 311 of 1658
REJ09B0261-0100