SH7785 Datasheet, PDF (775/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Clock Pulse Generator (CPG)
15.4.3 Frequency Display Register 1 (FRQMR1)
FRQMR1 is a 32-bit readable register that reads the division ratio of divider 2 for the CPU clock
(lck), the SuperHyway clock (SHck), the peripheral clock (Pck), the DDR clock (DDRck),the bus
clock (Bck), the GDTA clock (GAck), the DU clock (DUck), and the RAM clock (Uck).
FRQMR1 can only be accessed in longwords.
This register is initialized by only a power-on reset via the PRESET pin or a WDT overflow.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IFST3 IFST2 IFST1 IFST0 UFST3 UFST2 UFST1 UFST0 SFST3 SFST2 SFST1 SFST0 BFST3 BFST2 BFST1 BFST0
Initial value: 0
0
0
1
0
0
1
x
0
0
1
x
x
x
x
1
R/W: R R R R R R R R R R R R R R R R
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MFST3 MFST2 MFST1 MFST0 S2FST3 S2FST2 S2FST1 S2FST0 S3FST3 S3FST2 S3FST1 S3FST0 PFST3 PFST2 PFST1 PFST0
Initial value: 0
0
1
x
0
1
0
x
x
1
x
x
1
0
x
x
R/W: R R R R R R R R R R R R R R R R
Note: The initial value (x: a bit whose value is undefined) depends on the settings of mode pins
MODE0 to MODE4, MODE11, and MODE12 on a power-on reset via the PRESET pin.
See Table 15.3 or 15.4.
Initial
Bit
Bit Name Value R/W Description
31
IFST3
0
30
IFST2
0
29
IFST1
0
28
IFST0
1
R
Frequency division ratio of the CPU clock (Ick)
R
0001: × 1/2
R
0010: × 1/4
R
0011: × 1/6
27
UFST3
0
26
UFST2
0
25
UFST1
1
24
UFST0
x
R
Frequency division ratio of the RAM clock (Uck)
R
0010: × 1/4
R
0011: × 1/6
R
23
SFST3
0
22
SFST2
0
21
SFST1
1
20
SFST0
x
R
Frequency division ratio of the SuperHyway clock
R
(SHck)
R
0010: × 1/4
R
0011: × 1/6
Rev.1.00 Jan. 10, 2008 Page 745 of 1658
REJ09B0261-0100