SH7785 Datasheet, PDF (1338/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

26. Serial Sound Interface (SSI) Module
26.3.2 Status Register (SSISR)
SSISR is configured by status flags that indicate the operating status of the SSI module and bits
that indicate the current channel number and word number.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯
⎯ DMRQ UIRQ OIRQ IIRQ DIRQ ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value: ₀
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R R/W* R/W* R
RR
R
R
R
R
RR
R
Bit: 15 14 13 12 11 10 9
8
⎯⎯ ⎯ ⎯ ⎯ ⎯⎯ ⎯
Initial value: ₀
0
0
0
0
0
0
0
R/W: R R R R R R R R
7
6
⎯⎯
0
0
RR
5
4
3
2
1
0
⎯ ⎯ CHNO1 CHNO0 SWNO IDST
0
0
0
0
1
1
RRRRRR
Initial
Bit
Bit Name Value R/W Description
31 to 29 ⎯
0
R
Reserved
These bits are always read as an undefined value. The
write value should always be 0.
28
DMRQ 0
R
DMA Request Status Flag
This status flag allows the CPU to see the status of the
DMA request of SSI module.
TRMD = 0 (Receive Mode):
• If DMRQ = 1 then SSIRDR has unread data.
• If SSIRDR is read then DMRQ = 0 until there is new
unread data.
TRMD = 1 (Transmit Mode):
• If DMRQ = 1, SSITDR requests data to be written to
continue the transmission onto the audio serial bus.
• Once data is written to SSITDR then DMRQ = 0
until further transmit data is requested.
Rev.1.00 Jan. 10, 2008 Page 1308 of 1658
REJ09B0261-0100