SH7785 Datasheet, PDF(372/1692 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer

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SH7785 Datasheet, PDF (372/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

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10. Interrupt Controller (INTC)

Table 10.16 shows response time. The response time is the time until when the interrupt request

signal from the INTC to the CPU is negated. In this case, suppose that the setting values of the

following registers, INTMSK0, INTMSK1, INTMSK2, INT2MSKR, and INT2GPIC, are changed

from the interrupt enable state to the interrupt disable state.

Table 10.16 Response Time after Changing the Value of Interrupt Enable/Disable Registers

(Interrupt Enabled â Interrupt Disabled)

Number of States

Peripheral

IRL

IRQ

Modules

Remarks

Item

INTMSK1

INTMSK2

INTMSK0

INT2MSKR,

INT2GPIC

Registers that

enable/disable

interrupts

Priority

1Pcyc

determination

time

8Bcyc +

2Pcyc*

1Pcyc

4Pcyc

Note: * The IRL interrupt source that has been already retained inside cannot cancel the

interrupt request signal to the CPU even if the IRL interrupt source is masked.

Rev.1.00 Jan. 10, 2008 Page 342 of 1658

REJ09B0261-0100

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