SH7785 Datasheet, PDF (735/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
CHCR DMARS
DMA Transfer
RS[3:0] MID RID Request Source DMA Transfer Request Signal Source
Bus
Destination Mode
1000 001101 01 SCIF5 transmitter TXI (transmit FIFO data empty) Any
SCFTDR5 Cycle
steal
10 SCIF5 receiver RXI (receive FIFO data full) SCFRDR5 Any
Cycle
steal
010000 01 HAC0 transmitter Transmit data empty request Any
HACPCML0, Cycle
HACPCMR0 steal
10 HAC0 receiver
Unread receive data is present HACPCML0, Any
HACPCMR0
Cycle
steal
010001 01 HAC1 transmitter Transmit data empty request Any
HACPCML1, Cycle
HACPCMR1 steal
10 HAC1 receiver
Unread receive data is present HACPCML1, Any
HACPCMR1
Cycle
steal
010100 01 SIOF transmitter Transmit FIFO data empty
Any
request
SITDR
Cycle
steal
10 SIOF receiver Receive FIFO data full request SIRDR
Any
Cycle
steal
100000 11 FLCTL data part Transmit FIFO data empty
Any
transmitter
request
FLDTFIFO Cycle
steal
FLCTL data part Receive FIFO data full request FLDTFIFO Any
receiver
Cycle
steal
100001 11 FLCTL
Transmit FIFO data empty
Any
management
request
code part
transmitter
FLECFIFO Cycle
steal
FLCTL
Receive FIFO data full request FLECFIFO Any
management
code part receiver
Cycle
steal
100100 11 MMCIF data part FIFO write request
transmitter
Any
DR
Cycle
steal
MMCIF data part FIFO read request
receiver
DR
Any
Cycle
steal
101000 01 HSPI transmitter Transmit data
Any
SPTBR
Cycle
steal
10 HSPI receiver Receive data
SPRBR
Any
Cycle
steal
Rev.1.00 Jan. 10, 2008 Page 705 of 1658
REJ09B0261-0100