SH7785 Datasheet, PDF (222/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Memory Management Unit (MMU)
7.7.2 ITLB Data Array (TLB Compatible Mode)
The ITLB data array is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are
specified in the data field.
In the address field, bits [31:23] have the value H'F30 indicating ITLB data array and the entry is
specified by bits [9:8].
In the data field, bits [28:10] indicate PPN, bit [8] indicates V, bits [7] and [4] indicate SZ, bit [6]
indicates PR, bit [3] indicates C, and bit [1] indicates SH.
The following two kinds of operation can be used on ITLB data array:
1. ITLB data array read
PPN, V, SZ, PR, C, and SH are read into the data field from the ITLB entry corresponding to
the entry set in the address field.
2. ITLB data array write
PPN, V, SZ, PR, C, and SH specified in the data field are written to the ITLB entry
corresponding to the entry set in the address field.
31
24 23
10 9 8 7
210
Address field _{1 1 1 1 0 0 1 1 0 * * * * * * * * * * * * E * * * * * * 0 0}
31 30 29 28
Data field
PPN
10 9 8 7 6 5 4 3 2 1 0
V
C
PPN: Physical page number
V: Validity bit
E: Entry
SZ[1:0]: Page size bits
*: Don't care
SZ1 SZ0
PR: Protection key data
PR
SH
C: Cacheability bit
SH: Share status bit
: Reserved bits (write value should be 0,
and read value is undefined )
Figure 7.19 Memory-Mapped ITLB Data Array (TLB Compatible Mode)
Rev.1.00 Jan. 10, 2008 Page 192 of 1658
REJ09B0261-0100