SH7785 Datasheet, PDF (280/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. On-Chip Memory
9.2.3 OL memory Transfer Source Address Register 1 (LSA1)
When MMUCR.AT = 0 or RAMCR.RP = 0, the LSA1 specifies the transfer source physical
address for block transfer to page 1A or 1B in the OL memory.
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L1SADR
Initial value : 0 0 0
R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L1SADR
L1SSZ
Initial value :
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 29 —
28 to 10 L1SADR
9 to 6 —
Initial
Value R/W
All 0
R
Undefined R/W
All 0
R
Description
Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.
OL memory Page 1 Block Transfer Source Address
When MMUCR.AT = 0 or RAMCR.RP = 0, these bits
specify transfer source physical address for block
transfer to page 1A or 1B in the OL memory.
Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.
Rev.1.00 Jan. 10, 2008 Page 250 of 1658
REJ09B0261-0100