SH7785 Datasheet, PDF (1025/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
20.3.16 CL Frame Height Setting Register (CLHR)
CLHR is in the CL register block and sets the input image height in line units.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯⎯⎯⎯
CL_H
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ⎯ ⎯ ⎯ ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 12 ⎯
All 0 ⎯
Reserved
These bits are always read as 0. The write value should
always be 0.
11 to 0 CL_H
All 0 R/W Frame height setting
Should be set in line units.
Note: CL processing is prohibited when the setting is 0.
Rev.1.00 Jan. 10, 2008 Page 995 of 1658
REJ09B0261-0100