SH7785 Datasheet, PDF (900/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
19.3.15 Vertical Cycle Register (VCR)
The vertical cycle register (VCR) sets the vertical scan interval. The value is retained during
power-on reset and manual reset.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Internal update:
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
——————
VC
Initial value: 0
0
0
0
0
0 ——————————
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Internal update:
OOOOOOOOOO
Initial
Bit
Bit Name Value R/W
31 to 10 ⎯
All 0
R
9 to 0 VC
Undefined R/W
Internal
Update Description
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
Yes
Vertical Cycle
The vertical scan interval, including the vertical
blanking interval, should be set in raster line
units.
When in TV sync mode, the EXVSYNC rising-
edge detection interval time should be set. If not
detected within the interval, the result is
reflected in the TVR flag in DSSR.
Rev.1.00 Jan. 10, 2008 Page 870 of 1658
REJ09B0261-0100