SH7785 Datasheet, PDF (1661/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix
C. Pin Functions
C.1 Pin States
Table C.1 Pin States in Reset, Power-Down State, and Bus-Released State
Pin Name
(LSI level)
A[25:0]
D[31:24]
D[23:16]
D[15:0]
CS[6:0]
BACK/BSREQ
BREQ/BSACK
BS
R/W
RD/FRAME
RDY
WE0/REG
WE1
WE2/IORD
WE3/IOWR
Pin Name
Related
(Module level) Module I/O
A[25:0]
LBSC O
D[31:24] (default) LBSC I/O
Port F[7:0]
GPIO I/O
D[23:16] (default) LBSC I/O
Port G[7:0]
GPIO I/O
D[15:0]
CS[6:0]
LBSC I/O
LBSC O
BACK/BSREQ LBSC I/O
(default)
Port M0
GPIO I/O
BREQ/BSACK LBSC I/O
(default)
Port M1
BS
GPIO I/O
LBSC O
R/W
LBSC O
RD/FRAME
LBSC O
RDY
WE0/REG
LBSC I
LBSC O
WE1
LBSC O
WE2/IORD
LBSC O
WE3/IOWR
LBSC O
Reset
Power-
Module Bus
on
Manual Sleep Standby Release
PZ
K
K
⎯
PZ/Z
Z
K
K
⎯
Z
⎯
K
K
⎯
Z
Z
K
K
⎯
Z
⎯
K
K
⎯
Z
Z
K
K
⎯
Z
H(m)/ K
PZ(s) *¹
H*²
K
K
⎯
K
⎯
PZ/Z
O
⎯
K
K
⎯
O
PZ
K
K
⎯
I
⎯
K
H(m)/ K
PZ(s) *¹
H(m)/ K
PZ(s) *¹
H(m)/ K
PZ(s) *¹
PI
K
H(m)/ K
PZ(s) *¹
H(m)/ K
PZ(s) *¹
H(m)/ K
PZ(s) *¹
H(m)/ K
PZ(s) *¹
K
⎯
K
⎯
K
⎯
K
⎯
K
⎯
K
⎯
K
⎯
K
⎯
K
⎯
I
PZ/Z
PZ/Z
PZ/Z
I
PZ/Z
PZ/Z
PZ/Z
PZ/Z
Rev.1.00 Jan. 10, 2008 Page 1631 of 1658
REJ09B0261-0100