|
SH7785 Datasheet, PDF (1052/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
|
◁ |
20. Graphics Data Translation Accelerator (GDTA)
No. Operation Description
(2) Calculation of The following formulae are used to compute output positions (nth row and
output position below) (DDR2-SDRAM output address).
(nth row and Output address formulae for nth row and below
below)
⢠Y output target address
Calculation formula: Output frame Y point value (base point) + [(mbrow Ã
16 + n - 1) à (width + Y padding)] + [mbcol à 16]
Output frame Y pointer value (base point): MCOYPR setting address
mbrow: Calculated from MCCF setting
mbcol: Calculated from MCCF setting
width: Calculated from MCWR setting
Y padding: Calculated from MCYPR setting
Subsequently, data for 16 dots (= 16 bytes) is processed in succession
⢠U/V output target address
Calculation formula: Output frame U point value (base point) + [(mbrow Ã
8 + n - 1) à (width/2 + U padding)] + [mbcol à 8]
Output frame U pointer value (base point): MCOUPR setting address
mbrow: Calculated from MCCF setting
mbcol: Calculated from MCCF setting
width: Calculated from MCWR setting
U padding: Calculated from MCUVPR setting
Subsequently, data for 8 dots (= 8 bytes) is processed in succession
V pointer address is calculated using a formula similar to that for the U pointer
address.
Rev.1.00 Jan. 10, 2008 Page 1022 of 1658
REJ09B0261-0100
|
▷ |