SH7785 Datasheet, PDF (25/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24.4.1 Operations in MMC Mode................................................................................ 1209
24.5 MMCIF Interrupt Sources................................................................................................ 1239
24.6 Operations when Using DMA.......................................................................................... 1240
24.6.1 Operation in Read Sequence............................................................................. 1240
24.6.2 Operation in Write Sequence ............................................................................ 1250
24.7 Register Accesses with Little Endian Specification......................................................... 1261
Section 25 Audio Codec Interface (HAC) .................................................................. 1263
25.1 Features............................................................................................................................ 1263
25.2 Input/Output Pins ............................................................................................................. 1265
25.3 Register Descriptions ....................................................................................................... 1266
25.3.1 Control and Status Register (HACCR) ............................................................. 1269
25.3.2 Command/Status Address Register (HACCSAR) ............................................ 1271
25.3.3 Command/Status Data Register (HACCSDR).................................................. 1273
25.3.4 PCM Left Channel Register (HACPCML)....................................................... 1275
25.3.5 PCM Right Channel Register (HACPCMR) .................................................... 1277
25.3.6 TX Interrupt Enable Register (HACTIER)....................................................... 1278
25.3.7 TX Status Register (HACTSR)......................................................................... 1279
25.3.8 RX Interrupt Enable Register (HACRIER) ...................................................... 1281
25.3.9 RX Status Register (HACRSR) ........................................................................ 1282
25.3.10 HAC Control Register (HACACR) .................................................................. 1284
25.4 AC 97 Frame Slot Structure............................................................................................. 1286
25.5 Operation ......................................................................................................................... 1288
25.5.1 Receiver ............................................................................................................ 1288
25.5.2 Transmitter........................................................................................................ 1288
25.5.3 DMA................................................................................................................. 1289
25.5.4 Interrupts........................................................................................................... 1289
25.5.5 Initialization Sequence...................................................................................... 1290
25.5.6 Power-Down Mode........................................................................................... 1295
25.5.7 Notes................................................................................................................. 1295
25.5.8 Reference .......................................................................................................... 1295
Section 26 Serial Sound Interface (SSI) Module ...................................................... 1297
26.1 Features............................................................................................................................ 1297
26.2 Input/Output Pins ............................................................................................................. 1299
26.3 Register Descriptions ....................................................................................................... 1300
26.3.1 Control Register (SSICR) ................................................................................. 1301
26.3.2 Status Register (SSISR) .................................................................................... 1308
26.3.3 Transmit Data Register (SSITDR).................................................................... 1313
26.3.4 Receive Data Register (SSIRDR) ..................................................................... 1313
Rev.1.00 Jan. 10, 2008 Page xxv of xxx
REJ09B0261-0100