SH7785 Datasheet, PDF (1141/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. Serial I/O with FIFO (SIOF)
22.3.6 Receive Control Data Register (SIRCR)
SIRCR is a 32-bit readable/writable register that stores receive control data of the SIOF. The
setting of SIRCR is valid only when bits FL3 to FL0 in SIMDR are set to 1xxx (x: any value).
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIRC0[15:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SIRC1[15:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 16 SIRC0[15:0] Undefined R/W
15 to 0 SIRC1[15:0] Undefined R/W
Description
Control Channel 0 Receive Data
These bits store data received from the SIOF_RXD pin
as control channel 0 receive data. The position of the
control channel 0 data in the transmit or receive frame
depends on the value set the CD0A bit in SICDAR.
• These bits are valid when the CD0E bit in SICDAR
is set to 1.
Control Channel 1 Receive Data
These bits store data received from the SIOF_RXD pin
as control channel 1 receive data. The position of the
control 1 channel data in the transmit or receive frame
depends on the value set in the CD1A bit in SICDAR.
• These bits are valid when the CD1E bit in SICDAR
is set to 1.
Rev.1.00 Jan. 10, 2008 Page 1111 of 1658
REJ09B0261-0100