SH7785 Datasheet, PDF (680/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
Subsequently, after the PCIC requires the bus and transfer data and the request is permitted, the
priority changes as follows:
Device 0 > device 2 > device 3 > device 1 > PCIC
Then, after the device 3 requires the bus and transfer data and the request is permitted, the priority
changes as follows:
Device 0 > device 2 > device 1 > PCIC > device 3
(4) Interrupts
• The PCIC has 10 interrupts (these signals are connected to the INTC of this LSI)
• Interrupts are enabled/disabled and their priority levels are specified by the INTC of this LSI
• When the PCIC operates in normal mode, INTA output is available as an interrupt to the host
device on the PCI bus. The INTA pin can be set to be asserted or negated by the IOCS bit in
PCICR.
Table 13.6 Interrupt Priority
Signal
PCISERR
PCIINTA
PCIINTB
PCIINTC
PCIINTD
PCIEER
PCIPWD3
PCIPWD2
PCIPWD1
PCIPWD0
Interrupt Source
SERR assertion detected in host mode
PCI interrupt A (INTA) assertion detected in host mode
PCI interrupt B (INTB) assertion detected in host mode
PCI interrupt C (INTC) assertion detected in host mode
PCI interrupt D (INTD) assertion detected in host mode
A PCI error occurs. Generated by PCIIR and PCIAINT.
(Maskable)
Power state transition to D3. Generated by PCIPINT.
(Maskable)
Power state transition to D2. Generated by PCIPINT.
(Maskable)
Power state transition to D1. Generated by PCIPINT.
(Maskable)
Power state transition to D0. Generated by PCIPINT.
(Maskable)
INTEVT Priority
H'A00 High
H'A20
H'A40
H'A60
H'A80
H'AA0
H'AC0
H'AE0
Low
Rev.1.00 Jan. 10, 2008 Page 650 of 1658
REJ09B0261-0100