SH7785 Datasheet, PDF (807/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Watchdog Timer and Reset (WDT)
16.5.2 Power-On Reset by Watchdog Timer Overflow
The time period taken by power-on reset on watchdog timer overflow (WDT reset holding time) is
equal to or more than 40 cycles of the peripheral clock (Pck).
The transition time from watchdog timer overflow to the power-on reset state (WDT reset setup
time) is equal to or more than 40 cycles of the peripheral clock (Pck).
If the bus clock frequency has been changed from the initial value, the oscillation settling time of
PLL2 circuit and the time until the LSI resumes operation (WDT count up) are also required. In
this case, the WDT reset holding time is two peripheral clock (Pck) cycles or more.
(1) Power-On Reset Caused by Watchdog Timer Overflow during Normal Operation
The timing of indicating the reset state or normal operation on the STATUS[1:0] pins is
synchronous with the peripheral clock (Pck), and is therefore asynchronous with the clocks input
from the EXTAL pin and the CLKOUT pin.
EXTAL
input
CLKOUT
output
CLKOUTENB
output
WDT overflow
signal
STATUS[1:0]
output
LL (normal)
HH (reset)
LL (normal)
WDT reset setup time
PLL oscillation
settling time
WDT count up WDT reset
holding time
Figure 16.6 STATUS Output by Power-On Reset Caused by WDT Overflow
during Normal Operation
Rev.1.00 Jan. 10, 2008 Page 777 of 1658
REJ09B0261-0100