SH7785 Datasheet, PDF (393/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Local Bus State Controller (LBSC)
Table 11.5 Register Configuration (2)
Register Name
Abbrev.
Power-on Reset Manual Reset by Sleep by Deep Sleep by
by PRESET
WDT/Multiple SLEEP
SLEEP Command
Pin/WDT/H-UDI Exception
Command (DSLP = 1)
Memory Address Map
Select Register
MMSELR H'0000 0000
H'0000 0000
Retained Retained
Bus Control Register
BCR
H'00 0000
Retained
Retained Retained
CS0 Bus Control Register CS0BCR H'7777 77F0
Retained
Retained Retained
CS1 Bus Control Register CS1BCR H'7777 77F0
Retained
Retained Retained
CS2 Bus Control Register CS2BCR H'7777 77F0
Retained
Retained Retained
CS3 Bus Control Register CS3BCR H'7777 77F0
Retained
Retained Retained
CS4 Bus Control Register CS4BCR H'7777 77F0
Retained
Retained Retained
CS5 Bus Control Register CS5BCR H'7777 77F0
Retained
Retained Retained
CS6 Bus Control Register CS6BCR H'7777 77F0
Retained
Retained Retained
CS0 Wait Control
Register
CS0WCR H'7777 770F
Retained
Retained Retained
CS1 Wait Control
Register
CS1WCR H'7777 770F
Retained
Retained Retained
CS2 Wait Control
Register
CS2WCR H'7777 770F
Retained
Retained Retained
CS3 Wait Control
Register
CS3WCR H'7777 770F
Retained
Retained Retained
CS4 Wait Control
Register
CS4WCR H'7777 770F
Retained
Retained Retained
CS5 Wait Control
Register
CS5WCR H'7777 770F
Retained
Retained Retained
CS6 Wait Control
Register
CS6WCR H'7777 770F
Retained
Retained Retained
CS5 PCMCIA Control
Register
CS5PCR H'7700 0000
Retained
Retained Retained
CS6 PCMCIA Control
Register
CS6PCR H'7700 0000
Retained
Retained Retained
Rev.1.00 Jan. 10, 2008 Page 363 of 1658
REJ09B0261-0100