SH7785 Datasheet, PDF (1012/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
20.3.4 GA Interrupt Source Indication Clear Register (GACICR)
GACICR is in the GDTA common register block and clears interrupt source indication for each
module. Bits in this register are read as 0.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
MC_ CL_ MC_ CL_
ERCR ERCR ENCR ENCR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ W W W W
Bit
Bit Name
31 to 4 ⎯
3
MC_ERCR
2
CL_ERCR
1
MC_ENCR
0
CL_ENCR
Initial
Value
All 0
0
0
0
0
R/W Description
⎯ Reserved
These bits are always read as 0. The write value should
always be 0.
W Clears indication of an MC error interrupt (clears the
MC_ERR bit)
0: No effect
1: Clears error interrupt indication
W Clears indication of a CL error interrupt (clears the
CL_ERR bit)
0: No effect
1: Clears error interrupt indication
W Clears indication of an MC processing end interrupt
(clears the MC_END bit)
0: No effect
1: Clears processing end interrupt indication
W Clears indication of a CL processing end interrupt (clears
the CL_END bit)
0: No effect
1: Clears processing end interrupt indication
Rev.1.00 Jan. 10, 2008 Page 982 of 1658
REJ09B0261-0100