SH7785 Datasheet, PDF (522/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. DDR2-SDRAM Interface (DBSC2)
12.4.6 SDRAM Timing Register 1 (DBTR1)
The SDRAM timing register 1 (DBTR1) is a readable/writable register. It is initialized only upon
power-on reset.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TRP2 TRP1 TRP0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
R/W: R R R R R R R R R R R R R R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯ ⎯ ⎯ ⎯ ⎯ TRRD2 TRRD1 TRRD0 ⎯ ⎯ ⎯ ⎯ ⎯ TWR2 TWR1 TWR0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
R/W: R R R R R R/W R/W R/W R R R R R R/W R/W R/W
Bit
Bit Name
31 to 19 ⎯
Initial
Value
All 0
18 to 16 TRP2 to 001
TRP0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
R/W tRP (PRE-ACT/REF period) Setting Bits
These bits set the PRE-ACT minimum period constraint
for the same bank. These bits should be set according
to the DDR2-SDRAM specifications. The number of
cycles is the number of DDR clock cycles.
000: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
001: 2 cycles
010: 3 cycles
011: 4 cycles
100: 5 cycles
101: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
:
111: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
Rev.1.00 Jan. 10, 2008 Page 492 of 1658
REJ09B0261-0100