SH7785 Datasheet, PDF (79/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3. Instruction Set
Addressing Instruction
Mode
Format
GBR indirect @(disp:8,
with displace- GBR)
ment
Effective Address Calculation Method
Calculation
Formula
Effective address is register GBR contents with Byte: GBR +
8-bit displacement disp added. After disp is
disp → EA
zero-extended, it is multiplied by 1 (byte), 2 (word), _{Word: GBR +}
or 4 (longword), according to the operand size. _{disp × 2 → EA}
GBR
disp
(zero-extended)
Longword:
+
GBR
+ disp × 1/2/4
GBR + disp ×
4 → EA
×
Indexed GBR @(R0, GBR)
indirect
1/2/4
Effective address is sum of register GBR and R0
contents.
GBR
GBR + R0 →
EA
+
GBR + R0
R0
PC-relative @(disp:8, PC)
with
displacement
Effective address is PC + 4 with 8-bit displacement Word: PC + 4
disp added. After disp is zero-extended, it is
+ disp × 2 →
multiplied by 2 (word), or 4 (longword), according EA
to the operand size. With a longword operand,
the lower 2 bits of PC are masked.
Longword:
PC & H'FFFF
PC
FFFC + 4 +
disp × 4 → EA
&^*
H'FFFF FFFC
+
4
+
disp
(zero-extended)
×
PC + 4 + disp
×2
or PC &
H'FFFF FFFC
+ 4 + disp × 4
2/4
* _{With longword operand}
Rev.1.00 Jan. 10, 2008 Page 49 of 1658
REJ09B0261-0100