SH7785 Datasheet, PDF (349/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
(5) INT2B4: Detailed Interrupt Sources for the MMCIF
Module Bit
MMCIF 31 to 4
3
2
1
0
Name
⎯
FRDY
ERR
TRAN
FSTAT
Detailed Source
Description
Reserved
MMCIF interrupt sources are
These bits are read as 0 ^{indicated. This register indicates the}
and cannot be modified. ^{MMCIF interrupt sources even if the}
mask setting for MMCIF is made in
FIFO ready end interrupt _{the interrupt mask register.}
CRC error interrupt, data
timeout error interrupt,
or command timeout
error interrupt
Data response interrupt,
data transfer end
interrupt, command
response receive end
interrupt, command
transmit end interrupt, or
data busy end interrupt
FIFO empty interrupt or
FIFO full interrupt
(6) INT2B5: Detailed Interrupt Sources for the FLCTL
Module Bit
FLCTL 31 to 4
Name
⎯
3
FLTRQ1
2
FLTRQ0
1
FLTEND
0
FLSTE
Detailed Source
Description
Reserved
FLCTL interrupt sources are
These bits are read as ^{indicated. This register indicates the}
0 and cannot be
FLCTL interrupt sources even if the
modified.
mask setting for FLCTL is made in
FLCTL FLECFIFO
the interrupt mask register.
transfer request
interrupt
FLCTL TLDTFIFO
transfer request
interrupt
FLCTL transfer end
interrupt
FLCTL status error
interrupt or ready/busy
timeout error interrupt
Rev.1.00 Jan. 10, 2008 Page 319 of 1658
REJ09B0261-0100