SH7785 Datasheet, PDF (324/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
Initial
Bit
Name
Value R/W Description
23
IC007
0
22
IC006
0
21
IC005
0
20
IC004
0
R/W Clears masking of the
[When read]
interrupt source of IRL3 to _{Undefined values are}
IRL0 = HLLL (H'8).
read.
R/W Clears masking of the
[When written]
interrupt source of IRL3 to
IRL0 = HLLH (H'9).
0: No effect
1: Clears the
R/W Clears masking of the
corresponding interrupt
interrupt source of IRL3 to
mask (enables the
IRL0 = HLHL (H'A).
interrupt)
R/W Clears masking of the
interrupt source of IRL3 to
IRL0 = HLHH (H'B).
19
IC003
0
R/W Clears masking of the
interrupt source of IRL3 to
IRL0 = HHLL (H'C).
18
IC002
0
R/W Clears masking of the
interrupt source of IRL3 to
IRL0 = HHLH (H'D).
17
IC001
0
R/W Clears masking of the
interrupt source of IRL3 to
IRL0 = HHHL (H'E).
16
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
15
IC115
0
14
IC114
0
13
IC113
0
12
IC112
0
R/W Clears masking of the
[When read]
interrupt source of IRL7 to _{Undefined values are}
IRL4 = LLLL (H'0).
read.
R/W Clears masking of the
[When written]
interrupt source of IRL7 to
IRL4 = LLLH (H'1).
0: No effect
1: Clears the
R/W Clears masking of the
corresponding interrupt
interrupt source of IRL7 to
mask (enables the
IRL4 = LLHL (H'2).
interrupt)
R/W Clears masking of the
interrupt source of IRL7 to
IRL4 = LLHH (H'3).
Rev.1.00 Jan. 10, 2008 Page 294 of 1658
REJ09B0261-0100