SH7785 Datasheet, PDF (621/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
Bit
10
9
8
7
6
5 to 3
Initial
Bit Name Value
FTO
0
PFE
0
TBS
0
⎯
0
BMAM 0
⎯
xxx
R/W
Description
SH: R/W PCI TRDY/Control Enable
PCI: R Specifies the function that negates TRDY within 5
cycles before disconnection in a target access.
0: Disabled
1: Enabled
SH: R/W PCI Pre-Fetch Enable
PCI: R
Specifies whether pre-fetch is performed when a
target memory access is performed by an external
PCI device.
0: Disabled
1: Enabled
SH: R/W Byte Swap
PCI: R Specifies whether byte data is swapped when the PCI
bus is accessed.
0: No swap
1: Byte data is swapped
For details, see section 13.4.3 (5), Endian or
section 13.4.4 (6), Endian.
SH: R Reserved
PCI: R This bit is always read as 0. The write value should
always be 0.
SH: R/W Bus Master Arbitration
PCI: R
Controls the PCI bus arbitration mode of the PCIC
when the PCIC is in host mode. This bit is ignored
when the PCIC is in normal mode.
Note: For details, see section 13.4.5 (3), Arbitration.
0: Priority fixed mode (PCIC > device0 > device1 >
device2 > device3)
1: Pseudo-round-robin (the priority of the device that
has bus mastership is set to the lowest.)
SH: R
PCI: R
Reserved
These bits are always read as an undefined value.
The write value should always be 0.
Rev.1.00 Jan. 10, 2008 Page 591 of 1658
REJ09B0261-0100