SH7785 Datasheet, PDF (1179/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. Serial I/O with FIFO (SIOF)
(6) 16-bit Stereo Data (3)
Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.1
used for right-channel data, slot No.2 used for control channel 0 data, slot No.3 used for control
channel 1 data, and frame length = 128 bits
SIOF_SCK
SIOF_SYNC
SIOF_TXD
SIOF_RXD
1 frame
L-channel R-channel Control
Control
data
data
channel 0 channel 1
Slot No.0 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7
1 bit delay
Specifications: TRMD[1:0] = 00 or 10, REDG = 0,
FL[3:0] = 1110 (frame length: 128 bits),
TDLE = 1,
TDLA[3:0] = 0000, TDRE = 1, TDRA[3:0] = 0001, SYNCDL = 1
RDLE = 1,
RDLA[3:0] = 0000, RDRE = 1, RDRA[3:0] = 0001,
CD0E = 1,
CD0A[3:0] = 0010, CD1E = 1, CD1A[3:0] = 0011
Figure 22.18 Transmit and Receive Timing (16-Bit Stereo Data (3))
(7) 16-bit Stereo Data (4)
Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.2
used for right-channel data, slot No.1 used for control channel 0 data, slot No.3 used for control
channel 1 data, and frame length = 128 bits
1 frame
SIOF_SCK
SIOF_SYNC
SIOF_TXD
SIOF_RXD
L-channel Control R-channel Control
data
channel 0
data
channel 1
Slot No.0 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7
1 bit delay
Specifications: TRMD[1:0] = 00 or 10, REDG = 1,
FL[3:0] = 1110 (frame length: 128 bits)
TDLE = 1,
TDLA[3:0] = 0000, TDRE = 1,
TDRA[3:0] = 0010, SYNCDL = 1
RDLE = 1,
RDLA[3:0] = 0000, RDRE = 1,
RDRA[3:0] = 0010,
CD0E = 1,
CD0A[3:0] = 0001, CD1E = 1,
CD1A[3:0] = 0011
Figure 22.19 Transmit and Receive Timing (16-Bit Stereo Data (4))
Rev.1.00 Jan. 10, 2008 Page 1149 of 1658
REJ09B0261-0100