SH7785 Datasheet, PDF (1092/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

21. Serial Communication Interface with FIFO (SCIF)
21.3.9 FIFO Control Register n (SCFCR)
SCFCR is a register that performs data count resetting and trigger data number setting for transmit
and receive FIFO registers, and also contains a loopback test enable bit.
SCFCR can always be read from and written to by the CPU.
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
RST
RG2*¹
RST
RG1*¹
RST
RG0*¹
RTRG1 RTRG0
TTRG1
TTRG0
MCE*¹
TFCL
RFCL
LOOP
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 11 —
Initial
Value
All 0
10
RSTRG2*¹ 0
9
RSTRG1*¹ 0
8
RSTRG0*¹ 0
7
RTRG1 0
6
RTRG0 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W SCIF_RTS Output Active Trigger
R/W The SCIF_RTS signal becomes high when the number
R/W ^{of receive data stored in SCFRDR exceeds the trigger}
setting count shown below.
000:63
001:1
010:8
011:16
100:32
101:48
110:54
111:60
R/W Receive FIFO Data Count Trigger
R/W These bits are used to set the number of receive data
bytes that sets the RDF flag in SCFSR.
The RDF flag is set when the number of receive data
bytes in SCFRDR is equal to or greater than the trigger
setting count shown below.
00:1
01:16
10:32
11:48
Rev.1.00 Jan. 10, 2008 Page 1062 of 1658
REJ09B0261-0100