SH7785 Datasheet, PDF (1369/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 27.1 shows a block diagram of the FLCTL.
27. NAND Flash Memory Controller (FLCTL)
DMAC
DMA transfer
requests
(2 lines)
Peripheral bus
32
Peripheral bus interface
32 32
32
32
Registers
Details of interrupt source
• FLSTE (status error or ready busy
timeout error)
• FLTEND (transfer end)
• FLTRQ0 (FIFO0 transfer request)
• FLTRQ1 (FIFO1 transfer request)
Interrupt
control
QTSEL
FCKSEL
FIFO
256 bytes
Transmission/
reception
control
FCLK
×1, ×1/2,
×1/4
Peripheral clock
Pck
8
8
FLCTL
Flash interface
8
Control signal
NAND-type
flash memory
Figure 27.1 Block Diagram of FLCTL
Rev.1.00 Jan. 10, 2008 Page 1339 of 1658
REJ09B0261-0100