307013-003 Datasheet, PDF (99/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5 Functional Description
This chapter describes the functions and interfaces of the ICH7 family.
5.1
PCI-to-PCI Bridge (D30:F0)
The PCI-to-PCI bridge resides in PCI Device 30, Function 0 on bus #0. This portion of
the ICH7 implements the buffering and control logic between PCI and Direct Media
Interface (DMI). The arbitration for the PCI bus is handled by this PCI device. The PCI
decoder in this device must decode the ranges for the DMI. All register contents are
lost when core well power is removed.
Direct Media Interface (DMI) is the chip-to-chip connection between the Memory
Controller Hub / Graphics and Memory Controller Hub ((G)MCH) and I/O Controller Hub
7 (ICH7). This high-speed interface integrates advanced priority-based servicing
allowing for concurrent traffic and true isochronous transfer capabilities. Base
functionality is completely software transparent permitting current and legacy software
to operate normally.
To provide for true isochronous transfers and configurable Quality of Service (QoS)
transactions, the ICH7 supports two virtual channels on DMI: VC0 and VC1. These two
channels provide a fixed arbitration scheme where VC1 is the highest priority. VC0 is
the default conduit of traffic for DMI and is always enabled. VC1 must be specifically
enabled and configured at both ends of the DMI link (i.e., the ICH7 and (G)MCH).
Configuration registers for DMI, virtual channel support, and DMI active state power
management (ASPM) are in the RCRB space in the Chipset Config Registers
(Section 7).
5.1.1
PCI Bus Interface
The ICH7 PCI interface supports PCI Local Bus Specification, Revision 2.3, at 33 MHz.
The ICH7 integrates a PCI arbiter that supports up to six external PCI bus masters in
addition to the internal ICH7 requests.
5.1.2 PCI Bridge As an Initiator
The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge
generates the following cycle types:
Table 5-1.
PCI Bridge Initiator Cycle Types
Command
C/BE#
I/O Read/Write
Memory Read/Write
Configuration Read/Write
Special Cycles
2h/3h
6h/7h
Ah/Bh
1h
Notes
Non-posted
Writes are posted
Non-posted
Posted
5.1.2.1
Memory Reads and Writes
The bridge bursts memory writes on PCI that are received as a single packet from DMI.
Intel ^® ICH7 Family Datasheet
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