307013-003 Datasheet, PDF (577/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

EHCI Controller Registers (D29:F7)
13.2.3
USB 2.0-Based Debug Port Register
The Debug port’s registers are located in the same memory area, defined by the Base
Address Register (MEM_BASE), as the standard EHCI registers. The base offset for the
debug port registers (A0h) is declared in the Debug Port Base Offset Capability Register
at Configuration offset 5Ah (D29:F7:offset 5Ah). The specific EHCI port that supports
this debug capability (port 0) is indicated by a 4-bit field (bits 20–23) in the
HCSPARAMS register of the EHCI controller. The address map of the Debug Port
registers is shown in Table 13-4.
Table 13-4. Debug Port Register Address Map
MEM_BASE +
Offset
Mnemonic
Register Name
A0–A3h
A4–A7h
A8–ABh
AC–AFh
B0–B3h
CNTL_STS Control/Status
USBPID
USB PIDs
DATABUF[3:0] Data Buffer (Bytes 3:0)
DATABUF[7:4] Data Buffer (Bytes 7:4)
CONFIG
Configuration
Default
Type
00000000h
R/W, R/WC, RO,
WO
00000000h R/W, RO
00000000h R/W
00000000h R/W
00007F01h R/W
NOTES:
1.
All of these registers are implemented in the core well and reset by PLTRST#, EHC
HCRESET, and a EHC D3-to-D0 transition.
2.
The hardware associated with this register provides no checks to ensure that software
programs the interface correctly. How the hardware behaves when programmed
inappropriately is undefined.
13.2.3.1
CNTL_STS—Control/Status Register
Offset:
MEM_BASE + A0h
Default Value: 0000h
Attribute:
Size:
R/W, R/WC, RO, WO
32 bits
Bit
Description
31 Reserved
OWNER_CNT — R/W.
0 = Ownership of the debug port is NOT forced to the EHCI controller (Default)
30
1 = Ownership of the debug port is forced to the EHCI controller (i.e. immediately
taken away from the companion Classic USB Host controller) If the port was
already owned by the EHCI controller, then setting this bit has no effect. This bit
overrides all of the ownership-related bits in the standard EHCI registers.
29 Reserved
ENABLED_CNT — R/W.
0 = Software can clear this by writing a 0 to it. The hardware clears this bit for the
same conditions where the Port Enable/Disable Change bit (in the PORTSC
28
register) is set. (Default)
1 = Debug port is enabled for operation. Software can directly set this bit if the port is
already enabled in the associated PORTSC register (this is enforced by the
hardware).
27:17 Reserved
Intel ^® ICH7 Family Datasheet
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