307013-003 Datasheet, PDF (505/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
Bit
Description
17:16
PRIM_SIG_MODE — R/W. These bits are used to control mode of the Primary IDE
signal pins for mobile swap bay support.
If the PRS bit (Chipset Config Registers:Offset 3414h:bit 1) is 1, the reset states of bits
17:16 will be 01 (tri-state) instead of 00 (normal).
00 = Normal (Enabled)
01 = Tri-state (Disabled)
10 = Drive low (Disabled)
11 = Reserved
Fast Secondary Drive 1 Base Clock (FAST_SCB1) — R/W. This bit is used in
conjunction with the SCT1 bits (D31:F2:4Ah, bits 13:12) to enable/disable Ultra ATA/
100 timings for the Secondary Slave drive.
15
0 = Disable Ultra ATA/100 timing for the Secondary Slave drive.
1 = Enable Ultra ATA/100 timing for the Secondary Slave drive (overrides bit 3 in this
register).
Fast Secondary Drive 0 Base Clock (FAST_SCB0) — R/W. This bit is used in
conjunction with the SCT0 bits (D31:F2:4Ah, bits 9:8) to enable/disable Ultra ATA/100
timings for the Secondary Master drive.
14
0 = Disable Ultra ATA/100 timing for the Secondary Master drive.
1 = Enable Ultra ATA/100 timing for the Secondary Master drive (overrides bit 2 in this
register).
Fast Primary Drive 1 Base Clock (FAST_PCB1) — R/W. This bit is used in
conjunction with the PCT1 bits (D31:F2:4Ah, bits 5:4) to enable/disable Ultra ATA/100
timings for the Primary Slave drive.
13
0 = Disable Ultra ATA/100 timing for the Primary Slave drive.
1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this
register).
Fast Primary Drive 0 Base Clock (FAST_PCB0) — R/W. This bit is used in
conjunction with the PCT0 bits (D31:F2:4Ah, bits 1:0) to enable/disable Ultra ATA/100
timings for the Primary Master drive.
12
0 = Disable Ultra ATA/100 timing for the Primary Master drive.
1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this
register).
11:8 Reserved
7:4 Scratchpad (SP1). ICH7 does not perform any action on these bits.
Secondary Drive 1 Base Clock (SCB1) — R/W.
3 _{0 = 33 MHz base clock for Ultra ATA timings.}
1 = 66 MHz base clock for Ultra ATA timings
Secondary Drive 0 Base Clock (SCBO) — R/W.
2 0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
Primary Drive 1 Base Clock (PCB1) — R/W.
1 _{0 = 33 MHz base clock for Ultra ATA timings.}
1 = 66 MHz base clock for Ultra ATA timings
Primary Drive 0 Base Clock (PCB0) — R/W.
0 _{0 = 33 MHz base clock for Ultra ATA timings.}
1 = 66 MHz base clock for Ultra ATA timings
Intel ^® ICH7 Family Datasheet
505