307013-003 Datasheet, PDF (14/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

10.2
10.3
10.4
10.5
10.6
10.1.27FWH_SEL2—Firmware Hub Select 2 Register (LPC I/F—D31:F0) .................. 378
10.1.28FWH_DEC_EN1—Firmware Hub Decode Enable Register (LPC I/F—D31:F0) .. 378
10.1.29BIOS_CNTL—BIOS Control Register (LPC I/F—D31:F0) .............................. 381
10.1.30FDCAP—Feature Detection Capability ID (LPC I/F—D31:F0) ........................ 382
10.1.31FDLEN—Feature Detection Capability Length (LPC I/F—D31:F0) .................. 382
10.1.32FDVER—Feature Detection Version (LPC I/F—D31:F0) ................................ 382
10.1.33FDVCT—Feature Vector Register (LPC I/F—D31:F0) ................................... 383
10.1.34RCBA—Root Complex Base Address Register (LPC I/F—D31:F0) .................. 384
DMA I/O Registers (LPC I/F—D31:F0) ................................................................. 385
10.2.1 DMABASE_CA—DMA Base and Current Address
Registers (LPC I/F—D31:F0)................................................................... 386
10.2.2 DMABASE_CC—DMA Base and Current Count Registers (LPC I/F—D31:F0) ... 387
10.2.3 DMAMEM_LP—DMA Memory Low Page Registers (LPC I/F—D31:F0) ............. 387
10.2.4 DMACMD—DMA Command Register (LPC I/F—D31:F0) .............................. 388
10.2.5 DMASTA—DMA Status Register (LPC I/F—D31:F0)..................................... 388
10.2.6 DMA_WRSMSK—DMA Write Single Mask Register (LPC I/F—D31:F0) ............ 389
10.2.7 DMACH_MODE—DMA Channel Mode Register (LPC I/F—D31:F0) ................. 390
10.2.8 DMA Clear Byte Pointer Register (LPC I/F—D31:F0) ................................... 391
10.2.9 DMA Master Clear Register (LPC I/F—D31:F0) .......................................... 391
10.2.10DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0) ........................ 391
10.2.11DMA_WRMSK—DMA Write All Mask Register (LPC I/F—D31:F0)................... 392
Timer I/O Registers (LPC I/F—D31:F0) ............................................................... 392
10.3.1 TCW—Timer Control Word Register (LPC I/F—D31:F0) ............................... 393
10.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register
(LPC I/F—D31:F0) ................................................................................ 395
10.3.3 Counter Access Ports Register (LPC I/F—D31:F0) ...................................... 396
8259 Interrupt Controller (PIC) Registers (LPC I/F—D31:F0) ................................. 396
10.4.1 Interrupt Controller I/O MAP (LPC I/F—D31:F0) ........................................ 396
10.4.2 ICW1—Initialization Command Word 1 Register (LPC I/F—D31:F0) .............. 397
10.4.3 ICW2—Initialization Command Word 2 Register (LPC I/F—D31:F0) .............. 398
10.4.4 ICW3—Master Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0) ......................................................... 398
10.4.5 ICW3—Slave Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0) ......................................................... 399
10.4.6 ICW4—Initialization Command Word 4 Register (LPC I/F—D31:F0) .............. 399
10.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)
Register (LPC I/F—D31:F0) .................................................................... 400
10.4.8 OCW2—Operational Control Word 2 Register (LPC I/F—D31:F0) .................. 400
10.4.9 OCW3—Operational Control Word 3 Register (LPC I/F—D31:F0) .................. 401
10.4.10ELCR1—Master Controller Edge/Level Triggered Register (LPC I/F—D31:F0).. 402
10.4.11ELCR2—Slave Controller Edge/Level Triggered Register (LPC I/F—D31:F0) ... 403
Advanced Programmable Interrupt Controller (APIC)(D31:F0)................................ 404
10.5.1 APIC Register Map (LPC I/F—D31:F0) ...................................................... 404
10.5.2 IND—Index Register (LPC I/F—D31:F0) ................................................... 404
10.5.3 DAT—Data Register (LPC I/F—D31:F0) .................................................... 405
10.5.4 EOIR—EOI Register (LPC I/F—D31:F0) .................................................... 405
10.5.5 ID—Identification Register (LPC I/F—D31:F0) ........................................... 406
10.5.6 VER—Version Register (LPC I/F—D31:F0) ................................................. 406
10.5.7 REDIR_TBL—Redirection Table (LPC I/F—D31:F0)...................................... 407
Real Time Clock Registers (LPC I/F—D31:F0)....................................................... 409
10.6.1 I/O Register Address Map (LPC I/F—D31:F0) ............................................ 409
10.6.2 Indexed Registers (LPC I/F—D31:F0) ...................................................... 410
10.6.2.1 RTC_REGA—Register A (LPC I/F—D31:F0) .................................. 411
10.6.2.2 RTC_REGB—Register B (General Configuration) (LPC I/F—D31:F0). 412
10.6.2.3 RTC_REGC—Register C (Flag Register) (LPC I/F—D31:F0) ............. 413
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