307013-003 Datasheet, PDF (625/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
16.1.11 NABMBAR—Native Audio Bus Mastering Base Address
Register (Audio—D30:F2)
Address Offset: 14h–17h
Default Value: 00000001h
Lockable:
No
Attribute:
Size:
Power Well:
R/W, RO
32 bits
Core
The Native PCI Mode Audio function uses PCI Base Address register #1 to request a
contiguous block of I/O space that is to be used for the Native Mode Audio software
interface.
Note:
The DMA registers for S/PDIF* and Microphone In 2 cannot be addressed via this
address space. These DMA functions are only available from the new MBBAR register.
This register powers up as read only and only becomes write-able when the IOSE bit in
offset 41h is set.
Bit
Description
31:16 Hardwired to 0s
15:6
Base Address — R/W. These bits are used in the I/O space decode of the Native Audio
Bus Mastering interface registers. The number of upper bits that a device actually
implements depends on how much of the address space the device will respond to. For
AC '97 bus mastering, the upper 16 bits are hardwired to 0, while bits 15:6 are
programmable. This configuration yields a maximum
I/O block size of 64 bytes for this base address.
5:1 Reserved. Read as 0’s.
Resource Type Indicator (RTE) — RO. This bit defaults to 0 and changes to 1 if the
0 IOSE bit is set (D30:F2:Offset 41h, bit 0). When 1, this bit indicates a request for I/O
space.
16.1.12 MMBAR—Mixer Base Address Register (Audio—D30:F2)
Address Offset: 18h–1Bh
Default Value: 00000000h
Lockable:
No
Attribute:
Size:
Power Well:
R/W, RO
32 bits
Core
This BAR creates 512 bytes of memory space to signify the base address of the register
space. The lower 256 bytes of this space map to the same registers as the 256-byte I/
O space pointed to by NAMBAR. The lower 384 bytes are divided as follows:
• 128 bytes for the primary codec (offsets 00–7Fh)
• 128 bytes for the secondary codec (offsets 80–FFh)
• 128 bytes for the tertiary codec (offsets 100h–17Fh).
• 128 bytes of reserved space (offsets 180h–1FFh), returning all 0’s.
Bit
31:9
8:3
2:1
0
Description
Base Address — R/W. This field provides the lower 32-bits of the 512-byte memory
offset to use for decoding the primary, secondary, and tertiary codec’s mixer spaces.
Reserved. Read as 0s.
Type — RO. Hardwired to 00b to Indicate the base address exists in 32-bit address
space
Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for memory
space.
Intel ^® ICH7 Family Datasheet
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