307013-003 Datasheet, PDF (676/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.21 BCTRL—Bridge Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 3Eh–3Fh
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:12
11
10
Reserved
Discard Timer SERR# Enable (DTSE). Reserved per PCI Express* Base Specification,
Revision 1.0a
Discard Timer Status (DTS). Reserved per PCI Express* Base Specification, Revision
1.0a.
9
Secondary Discard Timer (SDT). Reserved per PCI Express* Base Specification,
Revision 1.0a.
8
Primary Discard Timer (PDT). Reserved per PCI Express* Base Specification, Revision
1.0a.
7
Fast Back to Back Enable (FBE). Reserved per PCI Express* Base Specification, Revision
1.0a.
6
Secondary Bus Reset (SBR) — R/W. This bit triggers a hot reset on the PCI Express*
port.
5 Master Abort Mode (MAM): Reserved per Express specification.
VGA 16-Bit Decode (V16) — R/W.
4
0 = VGA range is enabled.
1 = The I/O aliases of the VGA range (see BCTRL:VE definition below), are not enabled,
and only the base I/O ranges can be decoded
VGA Enable (VE)— R/W.
0 = The ranges below will not be claimed off the backbone by the root port.
3 ^{1 = The following ranges will be claimed off the backbone by the root port:}
— Memory ranges A0000h–BFFFFh
— I/O ranges 3B0h – 3BBh and 3C0h – 3DFh, and all aliases of bits 15:10 in any combination
of 1s
ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the
I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space.
2
0 = The root port will not block any forwarding from the backbone as described below.
1 = The root port will block any forwarding from the backbone to the device of I/O
transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to
3FFh).
SERR# Enable (SE) — R/W.
1
0 = The messages described below are not forwarded to the backbone.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages received are forwarded to
the backbone.
Parity Error Response Enable (PERE) — R/W.
0 = Poisoned write TLPs and completions indicating poisoned TLPs will not set the
0
SSTS.DPD (D28:F0/F1/F2/F3/F4/F5:1E, bit 8).
1 = Poisoned write TLPs and completions indicating poisoned TLPs will set the
SSTS.DPD (D28:F0/F1/F2/F3/F4/F5:1E, bit 8).
676
Intel ^® ICH7 Family Datasheet