307013-003 Datasheet, PDF (260/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Register and Memory Mapping
Table 6-4.
Memory Decode Ranges from Processor Perspective (Sheet 2 of 2)
Memory Range
FFD0 0000h–FFD7 FFFFh
FF90 0000h–FF97 FFFFh
FFD8 0000h–FFDF FFFFh
FF98 0000h–FF9F FFFFh
FFE0 000h–FFE7 FFFFh
FFA0 0000h–FFA7 FFFFh
FFE8 0000h–FFEF FFFFh
FFA8 0000h–FFAF FFFFh
FFF0 0000h–FFF7 FFFFh
FFB0 0000h–FFB7 FFFFh
FFF8 0000h–FFFF FFFFh
FFB8 0000h–FFBF FFFFh
FF70 0000h–FF7F FFFFh
FF30 0000h–FF3F FFFFh
FF60 0000h–FF6F FFFFh
FF20 0000h–FF2F FFFFh
FF50 0000h–FF5F FFFFh
FF10 0000h–FF1F FFFFh
FF40 0000h–FF4F FFFFh
FF00 0000h–FF0F FFFFh
4 KB anywhere in 4-GB
range
1 KB anywhere in 4-GB
range
512 B anywhere in 4-GB
range
256 B anywhere in 4-GB
range
512 B anywhere in 64-bit
addressing space
FED0 X000h–FED0 X3FFh
All other
Target
Firmware Hub (or
PCI)¹
Firmware Hub (or
PCI)¹
Firmware Hub (or
PCI)¹
Firmware Hub (or
PCI)¹
Firmware Hub (or
PCI)¹
Firmware Hub (or
PCI)¹
Firmware Hub (or
PCI)¹
Firmware Hub (or
PCI)¹
Firmware Hub (or
PCI)¹
Firmware Hub (or
PCI)¹
Integrated LAN
Controller²
USB EHCI
Controller ²
AC ’97 Host
Controller (Mixer)
AC ’97 Host
Controller (Bus
Master)
Intel^® High
Definition Audio
Host Controller
High Precision
Event Timers ³
PCI
Dependency/Comments
Bit 10 in Firmware Hub Decode Enable
register is set
Bit 11 in Firmware Hub Decode Enable
register is set
Bit 12 in Firmware Hub Decode Enable
register is set
Bit 13 in Firmware Hub Decode Enable
register is set
Bit 14 in Firmware Hub Decode Enable
register is set
Always enabled.
The top two, 64 KB blocks of this range can
be swapped, as described in Section 7.4.1.
Bit 3 in Firmware Hub Decode Enable register
is set
Bit 2 in Firmware Hub Decode Enable register
is set
Bit 1 in Firmware Hub Decode Enable register
is set
Bit 0 in Firmware Hub Decode Enable register
is set
Enable via BAR in Device 29:Function 0
(Integrated LAN Controller)
Enable via standard PCI mechanism (Device
29, Function 7)
Enable via standard PCI mechanism (Device
30, Function 2)
Enable via standard PCI mechanism (Device
30, Function 3)
Enable via standard PCI mechanism (Device
30, Function 1)
BIOS determines the “fixed” location which is
one of four, 1-KB ranges where X (in the first
column) is 0h, 1h, 2h, or 3h.
None
NOTES:
1.
PCI is the target when the Boot BIOS Destination selection bit is low (Chipset Config
Registers:Offset 3401:bit 3). When PCI selected, the Firmware Hub Decode Enable bits
have no effect.
2.
Only LAN cycles can be seen on PCI.
3.
Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High
Precision Event Timers. If attempted, the lock is not honored, which means potential
deadlock conditions may occur.
260
Intel ^® ICH7 Family Datasheet