307013-003 Datasheet, PDF (621/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
16.1.3
PCICMD—PCI Command Register (Audio—D30:F2)
Address Offset: 04h–05h
Default Value: 0000h
Lockable:
No
Attribute:
Size:
Power Well:
R/W, RO
16 bits
Core
PCICMD is a 16-bit control register. Refer to the PCI 2.3 specification for complete
details on each bit.
Bit
Description
15:11 Reserved. Read 0.
Interrupt Disable (ID) — R/W.
10 ^{0 = The INTx# signals may be asserted and MSIs may be generated.}
1 = The AC ‘97 controller’s INTx# signal will be de-asserted and it may not generate
MSIs.
9 Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.
8 SERR# Enable (SERR_EN) — RO. Not implemented. Hardwired to 0.
7 Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.
6 Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.
5 VGA Palette Snoop (VPS). Not implemented. Hardwired to 0.
4 Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to 0.
3 Special Cycle Enable (SCE). Not implemented. Hardwired to 0.
Bus Master Enable (BME) — R/W. Controls standard PCI bus mastering capabilities.
2 _{0 = Disable}
1 = Enable
Memory Space Enable (MSE) — R/W. Enables memory space addresses to the AC ’97
Audio controller.
1
0 = Disable
1 = Enable
I/O Space Enable (IOSE) — R/W. This bit controls access to the AC ’97 Audio
controller I/O space registers.
0 = Disable (Default).
0 ^{1 = Enable access to I/O space. The Native PCI Mode Base Address register should be}
programmed prior to setting this bit.
NOTE: This bit becomes writable when the IOSE bit in offset 41h is set. If at any point
software decides to clear the IOSE bit, software must first clear the IOS bit.
Intel ^® ICH7 Family Datasheet
621