307013-003 Datasheet, PDF (470/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

UHCI Controllers Registers
11.1.1
11.1.2
11.1.3
VID—Vendor Identification Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
Default Value:
00h–01h
8086h
Attribute:
Size:
RO
16 bits
Bit
Description
15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel
DID—Device Identification Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
Default Value:
02h–03h
UHCI #1 = See bit description
UHCI #2 = See bit description
UHCI #3 = See bit description
UHCI #4 = See bit description
Attribute:
Size:
RO
16 bits
Bit
15:0
Description
Device ID — RO. This is a 16-bit value assigned to the Intel^® ICH7 USB universal host
controllers. Refer to the Intel^® I/O Controller Hub 7 (ICH7) Family Specification Update
for the value of the Device ID Register.
PCICMD—PCI Command Register (USB—D29:F0/F1/F2/
F3)
Address Offset:
Default Value:
04h–05h
0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:11 Reserved
Interrupt Disable — R/W.
0 = Enable. The function is able to generate its interrupt to the interrupt controller.
10 1 = Disable. The function is not capable of generating interrupts.
NOTE: The corresponding Interrupt Status bit is not affected by the interrupt enable.
9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
8 SERR# Enable — RO. Reserved as 0.
7 Wait Cycle Control (WCC) — RO. Hardwired to 0.
6 Parity Error Response (PER) — RO. Hardwired to 0.
5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
3 Special Cycle Enable (SCE) — RO. Hardwired to 0.
Bus Master Enable (BME) — R/W.
2 0 = Disable
1 = Enable. Intel^® ICH7 can act as a master on the PCI bus for USB transfers.
1 Memory Space Enable (MSE) — RO. Hardwired to 0.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 ^{0 = Disable}
1 = Enable accesses to the USB I/O registers. The Base Address register for USB should
be programmed before this bit is set.
470
Intel ^® ICH7 Family Datasheet