307013-003 Datasheet, PDF (119/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.5.1.1
LPC Cycle Types
The ICH7 implements the following cycle types as described in Table 5-5
Table 5-5. LPC Cycle Types Supported
Cycle Type
I/O Read
I/O Write
DMA Read
(Desktop and
Mobile Only)
DMA Write
(Desktop and
Mobile Only)
Bus Master Read
Bus Master Write
Comment
1 byte only. Intel^® ICH7 breaks up 16- and 32-bit processor cycles into
multiple 8-bit transfers.
1 byte only. ICH7 breaks up 16- and 32-bit processor cycles into multiple
8-bit transfers.
Can be 1, or 2 bytes
Can be 1, or 2 bytes
Can be 1, 2, or 4 bytes. (See Note 1 below)
Can be 1, 2, or 4 bytes. (See Note 1 below)
NOTES:
1.
Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer
can be to any address. However, the 2-byte transfer must be word-aligned (i.e., with an
address where A0=0). A dword transfer must be dword-aligned (i.e., with an address
where A1 and A0 are both 0)
5.5.1.2
Start Field Definition
Table 5-6.
Start Field Bit Definitions
Bits[3:0]
Encoding
Definition
0000
0010
0011
1111
Start of cycle for a generic target
Grant for bus master 0
Grant for bus master 1
Stop/Abort: End of a cycle for a
target.
NOTE: All other encodings are RESERVED.
Intel ^® ICH7 Family Datasheet
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