307013-003 Datasheet, PDF (626/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
16.1.13 MBBAR—Bus Master Base Address Register
(Audio—D30:F2)
Address Offset: 1Ch–1Fh
Default Value: 00000000h
Lockable:
No
Attribute:
Size:
Power Well:
R/W, RO
32 bits
Core
This BAR creates 256-bytes of memory space to signify the base address of the bus
master memory space. The lower 64-bytes of the space pointed to by this register
point to the same registers as the MBBAR.
Bit
Description
31:8
Base Address — R/W. This field provides the I/O offset to use for decoding the PCM In,
PCM Out, and Microphone 1 DMA engines.
7:3 Reserved. Read as 0s.
2:1
Type — RO. Hardwired to 00b to indicate the base address exists in 32-bit address
space
0
Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for memory
space.
16.1.14 SVID—Subsystem Vendor Identification Register
(Audio—D30:F2)
Address Offset: 2Ch–2Dh
Default Value: 0000h
Lockable:
No
Attribute:
Size:
Power Well:
R/WO
16 bits
Core
The SVID register, in combination with the Subsystem ID register (D30:F2:2Eh),
enable the operating environment to distinguish one audio subsystem from the
other(s).
This register is implemented as write-once register. Once a value is written to it, the
value can be read back. Any subsequent writes will have no effect.
This register is not affected by the D3_HOT to D0 transition.
Bit
15:0
Subsystem Vendor ID — R/WO.
Description
626
Intel ^® ICH7 Family Datasheet