307013-003 Datasheet, PDF (20/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

14.2.4 XMIT_SLVA—Transmit Slave Address Register (SMBUS—D31:F3)................. 593
14.2.5 HST_D0—Host Data 0 Register (SMBUS—D31:F3)..................................... 593
14.2.6 HST_D1—Host Data 1 Register (SMBUS—D31:F3)..................................... 593
14.2.7 Host_BLOCK_DB—Host Block Data Byte Register (SMBUS—D31:F3) ............ 594
14.2.8 PEC—Packet Error Check (PEC) Register (SMBUS—D31:F3) ........................ 594
14.2.9 RCV_SLVA—Receive Slave Address Register (SMBUS—D31:F3) ................... 595
14.2.10SLV_DATA—Receive Slave Data Register (SMBUS—D31:F3) ........................ 595
14.2.11AUX_STS—Auxiliary Status Register (SMBUS—D31:F3).............................. 595
14.2.12AUX_CTL—Auxiliary Control Register (SMBUS—D31:F3) ............................. 596
14.2.13SMLINK_PIN_CTL—SMLink Pin Control Register (SMBUS—D31:F3) .............. 596
14.2.14SMBUS_PIN_CTL—SMBUS Pin Control Register (SMBUS—D31:F3) ............... 597
14.2.15SLV_STS—Slave Status Register (SMBUS—D31:F3)................................... 597
14.2.16SLV_CMD—Slave Command Register (SMBUS—D31:F3)............................. 598
14.2.17NOTIFY_DADDR—Notify Device Address Register (SMBUS—D31:F3) ............ 598
14.2.18NOTIFY_DLOW—Notify Data Low Byte Register (SMBUS—D31:F3)............... 599
14.2.19NOTIFY_DHIGH—Notify Data High Byte Register (SMBUS—D31:F3) ............. 599
15 IDE Controller Registers (D31:F1).......................................................................... 601
15.1 PCI Configuration Registers (IDE—D31:F1) ......................................................... 601
15.1.1 VID—Vendor Identification Register (IDE—D31:F1).................................... 602
15.1.2 DID—Device Identification Register (IDE—D31:F1).................................... 602
15.1.3 PCICMD—PCI Command Register (IDE—D31:F1)....................................... 602
15.1.4 PCISTS — PCI Status Register (IDE—D31:F1)........................................... 603
15.1.5 RID—Revision Identification Register (IDE—D31:F1).................................. 603
15.1.6 PI—Programming Interface Register (IDE—D31:F1)................................... 604
15.1.7 SCC—Sub Class Code Register (IDE—D31:F1) .......................................... 604
15.1.8 BCC—Base Class Code Register (IDE—D31:F1) ......................................... 604
15.1.9 CLS—Cache Line Size Register (IDE—D31:F1) .......................................... 604
15.1.10PMLT—Primary Master Latency Timer Register (IDE—D31:F1) ..................... 605
15.1.11PCMD_BAR—Primary Command Block Base Address
Register (IDE—D31:F1) ......................................................................... 605
15.1.12PCNL_BAR—Primary Control Block Base Address Register (IDE—D31:F1) ..... 605
15.1.13SCMD_BAR—Secondary Command Block Base Address
Register (IDE D31:F1) ........................................................................... 606
15.1.14SCNL_BAR—Secondary Control Block Base Address
Register (IDE D31:F1) ........................................................................... 606
15.1.15BM_BASE — Bus Master Base Address Register (IDE—D31:F1) ................... 607
15.1.16IDE_SVID — Subsystem Vendor Identification (IDE—D31:F1) ..................... 607
15.1.17IDE_SID — Subsystem Identification Register (IDE—D31:F1) ..................... 607
15.1.18INTR_LN—Interrupt Line Register (IDE—D31:F1) ...................................... 608
15.1.19INTR_PN—Interrupt Pin Register (IDE—D31:F1)........................................ 608
15.1.20IDE_TIMP — IDE Primary Timing Register (IDE—D31:F1) ........................... 608
15.1.21IDE_TIMS — IDE Secondary Timing Register (IDE—D31:F1) ....................... 610
15.1.22SLV_IDETIM—Slave (Drive 1) IDE Timing Register
(IDE—D31:F1) (Desktop and Mobile Only) ............................................... 610
15.1.23SDMA_CNT—Synchronous DMA Control Register (IDE—D31:F1) .................. 611
15.1.24SDMA_TIM—Synchronous DMA Timing Register (IDE—D31:F1) ................... 611
15.1.25IDE_CONFIG—IDE I/O Configuration Register (IDE—D31:F1)...................... 612
15.1.26ATC—APM Trapping Control Register (IDE—D31:F1)................................... 614
15.1.27ATS—APM Trapping Status Register (IDE—D31:F1).................................... 614
15.2 Bus Master IDE I/O Registers (IDE—D31:F1) ....................................................... 615
15.2.1 BMICP—Bus Master IDE Command Register (IDE—D31:F1) ........................ 615
15.2.2 BMISP—Bus Master IDE Status Register (IDE—D31:F1) ............................. 616
15.2.3 BMIDP—Bus Master IDE Descriptor Table Pointer Register (IDE—D31:F1) ..... 617
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Intel ^® ICH7 Family Datasheet