307013-003 Datasheet, PDF (538/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.3.2.8
PxTFD—Port [3:0] Task File Data Register (D31:F2)
Address Offset:
Default Value:
Port 0: ABAR + 120h
Attribute:
RO
Port 1: ABAR + 1A0h (ICH7R and ICH7DH Only)
Port 2: ABAR + 220h
Port 3: ABAR + 2A0h (ICH7R and ICH7DH Only)
0000007Fh
Size:
32 bits
This is a 32-bit register that copies specific fields of the task file when FISes are
received. The FISes that contain this information are:
D2H Register FIS
PIO Setup FIS
Set Device Bits FIS
Bit
Description
31:16 Reserved
15:8 Error (ERR) — RO. Contains the latest copy of the task file error register.
Status (STS) — RO. Contains the latest copy of the task file status register. Fields of
note in this register that affect AHCI.
Bit
7
6:4
7:0
3
2:1
0
Field
BSY
N/A
DRQ
N/A
ERR
Definition
Indicates the interface is busy
Not applicable
Indicates a data transfer is
requested
Not applicable
Indicates an error during the
transfer
12.3.2.9
PxSIG—Port [3:0] Signature Register (D31:F2)
Address Offset:
Default Value:
Port 0: ABAR + 124h
Attribute:
RO
Port 1: ABAR + 1A4h (ICH7R and ICH7DH Only)
Port 2: ABAR + 224h
Port 3: ABAR + 2A4h (ICH7R and ICH7DH Only)
FFFFFFFFh
Size:
32 bits
This is a 32-bit register which contains the initial signature of an attached device when
the first D2H Register FIS is received from that device. It is updated once after a reset
sequence.
Bit
Description
31:0
Signature (SIG) — RO. Contains the signature received from a device on the first D2H
register FIS. The bit order is as follows:
Bit
Field
31:24 LBA High Register
23:16 LBA Mid Register
15:8
LBA Low Register
7:0
Sector Count Register
538
Intel ^® ICH7 Family Datasheet