307013-003 Datasheet, PDF (453/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.8.3.16 GPE_CNTL— General Purpose Control Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE +42h
00h
No
Resume
Attribute:
Size:
Usage:
R/W
8-bit
ACPI or Legacy
Bit
Description
7:2 Reserved
SWGPE_CTRL— R/W. This bit allows software to control the assertion of SWGPE_STS
bit. This bit is used by hardware as the level input signal for the SWGPE_STS bit in the
1
GPE0_STS register. When SWGPE_CTRL is 1, SWGPE_STS will be set to 1, and writes to
SWGPE_STS with a value of 1 to clear SWGPE_STS will result in SWGPE_STS being set
back to 1 by hardware. When SWGPE_CTRL is 0, writes to SWGPE_STS with a value of
1 will clear SWGPE_STS to 0.
THRM#_POL — R/W. This bit controls the polarity of the THRM# pin needed to set the
THRM_STS bit.
0
0 = Low value on the THRM# signal will set the THRM_STS bit.
1 = HIGH value on the THRM# signal will set the THRM_STS bit.
Intel ^® ICH7 Family Datasheet
453