307013-003 Datasheet, PDF (280/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Chipset Configuration Registers
7.1.36
TRSR—Trap Status Register
Offset Address: 1E00–1E03h
Default Value: 00000000h
Attribute:
Size:
R/WC, RO
32-bit
7.1.37
Bit
31:4
3:0
Description
Reserved
Cycle Trap SMI# Status (CTSS) — R/WC. These bits are set by hardware when the
corresponding Cycle Trap register is enabled and a matching cycle is received (and
trapped). These bits are OR’ed together to create a single status bit in the Power
Management register space.
Note that the SMI# and trapping must be enabled in order to set these bits.
These bits are set before the completion is generated for the trapped cycle, thereby
ensuring that the processor can enter the SMI# handler when the instruction
completes. Each status bit is cleared by writing a 1 to the corresponding bit location
in this register.
TRCR—Trapped Cycle Register
Offset Address: 1E10–1E17h
Default Value: 0000000000000000h
Attribute:
Size:
RO
64-bit
This register saves information about the I/O Cycle that was trapped and generated the
SMI# for software to read.
7.1.38
Bit
63:25
24
23:20
19:16
15:2
1:0
Description
Reserved
Read/Write# (RWI) — RO.
0 = Trapped cycle was a write cycle.
1 = Trapped cycle was a read cycle.
Reserved
Active-high Byte Enables (AHBE) — RO. This is the DWord-aligned byte enables
associated with the trapped cycle. A 1 in any bit location indicates that the
corresponding byte is enabled in the cycle.
Trapped I/O Address (TIOA) — RO. This is the DWord-aligned address of the
trapped cycle.
Reserved
TWDR—Trapped Write Data Register
Offset Address: 1E18–1E1Fh
Default Value: 0000000000000000h
Attribute:
Size:
RO
64-bit
This register saves the data from I/O write cycles that are trapped for software to read.
Bit
63:32
31:0
Description
Reserved
Trapped I/O Data (TIOD) — RO. DWord of I/O write data. This field is undefined
after trapping a read cycle.
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Intel ^® ICH7 Family Datasheet