307013-003 Datasheet, PDF (694/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.46 RPDCGEN - Root Port Dynamic Clock Gating Enable
(PCI Express-D28:F0/F1/F2/F3/F4/F5) (Mobile Only)
Address Offset: E1h
Default Value: 00h
Attribute:
Size:
R/W
8-bits
Bits
7:4
3
2
1
0
Description
Reserved. RO
Shared Resource Dynamic Link Clock Gating Enable (SRDLCGEN) — RW.
0 = Disables dynamic clock gating of the shared resource link clock domain.
1 = Enables dynamic clock gating on the root port shared resouce link clock domain.
Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for
ports 5–6.
Shared Resource Dynamic Backbone Clock Gate Enable (SRDBCGEN) — RW.
0 = Disables dynamic clock gating of the shared resource backbone clock domain.
1 = Enables dynamic clock gating on the root port shared resouce backbone clock
domain.
Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for
ports 5–6.
Root Port Dynamic Link Clock Gate Enable (RPDLCGEN) — RW.
0 = Disables dynamic clock gating of the root port link clock domain.
1 = Enables dynamic clock gating on the root port link clock domain.
Root Port Dynamic Backbone Clock Gate Enable (RPDBCGEN) — RW.
0 = Disables dynamic clock gating of the root port backbone clock domain.
1 = Enables dynamic clock gating on the root port backbone clock domain.
18.1.47 IPWS—Intel^® PRO/Wireless 3945ABG Status
(PCI Express—D28:F0/F1/F2/F3/F4/F5) (Mobile Only)
Address Offset: E2h–E3h
Default Value: 0007h
Attribute:
Size:
RO
16 bits
Bit
Description
15
Intel PRO/Wireless 3945ABG Status (IPWSTAT) — RO. This bit is set if the link
has trained to L0 in Intel PRO/Wireless 3945ABG mode.
14:0 Reserved
694
Intel ^® ICH7 Family Datasheet