307013-003 Datasheet, PDF (467/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.10.7 GP_IO_SEL2—GPIO Input/Output Select 2
Register[63:32]
Offset Address: GPIOBASE +34h
Default Value: 000000F0h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
32-bit
CPU I/O for 17, Core for
16, 7:0
Bit
Description
31:18,
15:8
Always 0. No corresponding GPIO.
17:16,
7:0
GP_IO_SEL2[49:48, 39:32] — R/W.
0 = GPIO signal is programmed as an output.
1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL2 register) is
programmed as an input.
10.10.8 GP_LVL2—GPIO Level for Input or Output 2
Register[63:32]
Offset Address: GPIOBASE +38h
Default Value: 00030003h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
32-bit
CPU I/O for 17, Core for
16:0
Bit
Description
31:18,
15:8
Reserved. Read-only 0
17:16,
7:0
GP_LVL[49:48, 39:32] — R/W.
If GPIO[n] is programmed to be an output (via the corresponding bit in the GP_IO_SEL
register), then the corresponding GP_LVL[n] bit can be updated by software to drive a
high or low value on the output pin. 1 = high, 0 = low.
If GPIO[n] is programmed as an input, then the corresponding GP_LVL bit reflects the
state of the input signal (1 = high, 0 = low.) and writes will have no effect.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have no
effect. The value reported in this register is undefined when programmed as native
mode.
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Intel ^® ICH7 Family Datasheet
467