307013-003 Datasheet, PDF (550/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

EHCI Controller Registers (D29:F7)
13.1.9
PMLT—Primary Master Latency Timer Register
(USB EHCI—D29:F7)
Address Offset: 0Dh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
Master Latency Timer Count (MLTC) — RO. Hardwired to 00h. Because the EHCI
7:0 controller is internally implemented with arbitration on an interface (and not PCI), it
does not need a master latency timer.
13.1.10 MEM_BASE—Memory Base Address Register
(USB EHCI—D29:F7)
Address Offset: 10h–13h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:10
Base Address — R/W. Bits [31:10] correspond to memory address signals [31:10],
respectively. This gives 1-KB of locatable memory space aligned to 1-KB boundaries.
9:4 Reserved
3 Prefetchable — RO. Hardwired to 0 indicating that this range should not be prefetched.
2:1
Type — RO. Hardwired to 00b indicating that this range can be mapped anywhere
within 32-bit address space.
0
Resource Type Indicator (RTE) — RO. Hardwired to 0 indicating that the base address
field in this register maps to memory space.
13.1.11 SVID—USB EHCI Subsystem Vendor ID Register
(USB EHCI—D29:F7)
Address Offset: 2Ch–2Dh
Default Value: XXXXh
Reset:
None
Attribute:
Size:
R/W (special)
16 bits
Bit
Description
15:0
Subsystem Vendor ID (SVID) — R/W (special). This register, in combination with the
USB 2.0 Subsystem ID register, enables the operating system to distinguish each
subsystem from the others.
NOTE: Writes to this register are enabled when the WRT_RDONLY bit (D29:F7:80h, bit
0) is set to 1.
550
Intel ^® ICH7 Family Datasheet